1. Field of the Invention
This invention relates to electronic storage devices, particularly to dynamic random access memory (DRAM) circuits.
2. Description of the Background Art
DRAMs are used widely in various electronic systems for storing large amounts of digital information. However, as such electronic systems operate at faster processing speeds, the access time for reading or writing data to or from DRAMs becomes a significant factor in the design of high-performance electronic systems.
Hence, various techniques are used for improving DRAM access times. One approach known as "nibble mode" significantly reduces access time delays by configuring a DRAM to access a series of four sequential bits in rapid succession after a first bit is accessed. Similarly, in an approach known as "burst mode," a full page or row of bits are accessed after the first bit is accessed. These approaches improve DRAM access time by essentially eliminating address re-loading delays associated with accessing each subsequent bit. Typically, neither normal nor burst/nibble mode is selectable by certain control signals.
Current nibble and burst mode techniques, however, generally operate under special modes and are thus limited to operating with asynchronous clock and address signals to access data bits. It would be desirable, therefore, to provide an improved approach in reducing DRAM access time without such asynchronous addressing overhead and particularly to provide an improved scheme for selecting operating modes.